16-channel signal acquisition and processing module
The 16-channel signal acquisition and processing module employs two Zynq UltraScale+ XCZU47DR‑2FFVG1517I devices, enabling four DAC channels and sixteen ADC channels. It features expandable I/O ports and DDR4 memory, making it suitable for a wide range of programmable applications. The ADC’s 16 channels are synchronized—equivalent to synchronization between two RFSoC chips (and across multiple boards)—which primarily involves the design of a complex clock topology. The overall clock architecture uses a single PLL (LMK04828) to supply clocks to both RFSoCs, with multi‑channel synchronization achieved via the RFSoC’s internal MTS functionality. The board is equipped with eight QSFP28 optical ports and integrates Ethernet, DDR4, an SD card slot, and a USB debugging port.
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Zynq UltraScale+ RFSOC Development Board
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- Commodity name: 16-channel signal acquisition and processing module
The 16-channel signal acquisition and processing module employs two Zynq UltraScale+ XCZU47DR‑2FFVG1517I devices, enabling four DAC channels and sixteen ADC channels. It features expandable I/O ports and DDR4 memory, making it suitable for a wide range of programmable applications. The ADC’s 16 channels are synchronized—equivalent to synchronization between two RFSoC chips (and across multiple boards)—which primarily involves the design of a complex clock topology. The overall clock architecture uses a single PLL (LMK04828) to supply clocks to both RFSoCs, with multi‑channel synchronization achieved via the RFSoC’s internal MTS functionality. The board is equipped with eight QSFP28 optical ports and integrates Ethernet, DDR4, an SD card slot, and a USB debugging port.
The 16-channel signal acquisition and processing module employs two Zynq UltraScale+ XCZU47DR‑2FFVG1517I devices, enabling four DAC channels and sixteen ADC channels. It features expandable I/O ports and DDR4 memory, making it suitable for a wide range of programmable applications. The ADC’s 16 channels are synchronized—equivalent to synchronization between two RFSoC chips (or across multiple boards)—which primarily involves the design of a complex clock topology. The overall clock architecture uses a single PLL (LMK04828) to supply clocks to both RFSoCs, with multi‑channel synchronization achieved via the RFSoC’s internal MTS functionality. The board is equipped with eight QSFP28 optical ports and integrates Ethernet, DDR4, an SD card slot, and a USB debugging port.
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Performance Metrics
FPGA chip
● 2 Zynq UltraScale+ XCZU47DR-2FFVG1517I chips
RF interface (single 47DR)
● X8 ADC (14-bit, 5 GSPS) ports
● X2 DAC (14-bit, 9.85 GSPS) ports
Memory (single chip 47DR)
● PS 4xDDR4 (4GB, 64-bit, 2400 MT/s)
● PL 2xDDR4(4GB,64bit, 2400MT/s)
Board power supply
● ATX power supply connector (12V, 5A)
Ambient temperature requirements
● 0~70℃
PS (single unit 47DR)
● 2x QSPI Flash
● 1x Micro SD slot
● 1x Micro USB
● 1×10/100/1000 Ethernet RGMII (RJ45) network port
PL (single unit 47DR)
● 4x QSFP28 400G optical ports
● 4X LVDS
● 10X TTL
● 1X Digital CLK
Size
● 220mm X 285mm
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