RF-PYNQ Starboard RF Development Board
IW_ZU48DR_QSFPX4_8T8R is a software-defined radio development platform built around the Zynq UltraScale+ RFSoC ZU48DR FPGA. It is fully compatible with AMD RFSoC‑PYNQ 4×2. RFSoC‑PYNQ is an extension of PYNQ, supporting AMD‑Xilinx Zynq RFSoC family devices. The RFSoC introduces a new class of integrated circuit architectures for the communications and instrumentation markets, combining high‑precision ADCs and DACs operating at gigasamples per second (GSPS) with a programmable heterogeneous computing engine. RFSoC‑PYNQ provides RFSoC users with Python APIs, libraries and drivers, example overlays and designs, tutorials, and other resources.
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Zynq UltraScale+ RFSOC Development Board
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- Commodity name: RF-PYNQ Starboard RF Development Board
IW_ZU48DR_QSFPX4_8T8R is a software-defined radio development platform built around the Zynq UltraScale+ RFSoC ZU48DR FPGA. It is fully compatible with AMD RFSoC‑PYNQ 4×2. RFSoC‑PYNQ is an extension of PYNQ, supporting AMD‑Xilinx Zynq RFSoC family devices. The RFSoC introduces a new class of integrated circuit architectures for the communications and instrumentation markets, combining high‑precision ADCs and DACs operating at gigasamples per second (GSPS) with a programmable heterogeneous computing engine. RFSoC‑PYNQ provides RFSoC users with Python APIs, libraries and drivers, example overlays and designs, tutorials, and other resources.
IW_ZU48DR_QSFPX4_8T8R is a software-defined radio development platform built around the Zynq UltraScale+ RFSoC ZU48DR FPGA. It is fully compatible with AMD RFSoC‑PYNQ 4×2. RFSoC‑PYNQ is an extension of PYNQ, supporting AMD‑Xilinx Zynq RFSoC family devices. The RFSoC introduces a new class of integrated circuit architectures for the communications and instrumentation markets, combining high‑precision ADCs and DACs operating at gigasamples per second (GSPS) with a programmable heterogeneous computing engine. RFSoC‑PYNQ provides RFSoC users with Python APIs, libraries and drivers, example overlays and designs, tutorials, and other resources.
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Performance Metrics
FPGA chip
● XCZU48DR-L2FSVG1517I
RF interface
● x8ADC (14-bit, 5 GSPS) ports
● x8DAC (14-bit, 9.85 GSPS) ports
Optical port
● 4xQSFP 100G optical ports
Memory
● PS 4xDDR4(4GB,64bit)
● PL 4xDDR4(4GB,64bit)
Board power supply
● The power supply interface uses a 12V power input.
Size
●260.0604mm*209.9996mm
PS-side interface
● 2x USB 3.0 Port
● 1x 10/100/1000 Ethernet RGMII (RJ45) network port
● 1x Micro SD Card
● 1x DisplayPort
● 1x OLED
PL-side interface
● 1x SYZYGY interface
● 1x PMOD interface
● 8-channel ADC (14-bit, 5 GSPS) port
● 8-channel DAC (14-bit, 9.85 GSPS) port
Power consumption
● 60W (actual measured value, depending on the application)
Ambient temperature requirements
● Operating temperature: -40°C to 70°C
RFSoC-PYNQ Features
● The PYNQ framework, featuring Jupyter Lab, offers exceptional ease of use.
● Python API for RFSoC clocks and data converters
● Supports RFSoC Gen 1, Gen 2, and Gen 3 devices, including the AMD University Program RFSoC 4x2.
● A complete end-to-end reference design, including a spectrum analyzer and a software-defined radio (see the overlay layer).
● Open-source educational resources, including textbooks, notebooks, and design examples
● GitHub-hosted repositories for all project materials
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