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Low-Cost 8-Channel GEN3 Algorithm Verification and Evaluation Board

IWZU47DR_BL1156_8T8R is based on the Zynq UltraScale+ RFSoC family device XCZU47DRFFVE1156 (hereinafter referred to as XCZU47DR). This series integrates key subsystems for multi‑band, multi‑standard cellular communications and cable infrastructure (DOCSIS) into a single SoC platform, featuring a feature‑rich 64‑bit quad‑core Arm® Cortex‑A53 processor and a dual‑core Arm Cortex‑R5F processing system. Zynq UltraScale+ devices combine an ARM Cortex‑A53 processing subsystem, UltraScale+ programmable logic, and industry‑leading signal‑processing bandwidth, enabling the implementation of complete RF signal chains to meet the demanding requirements of high‑performance RF applications such as wireless communications, cable TV access, and test & measurement.

Model: IWZU47DR_BL1156_8T8R

Category:

Zynq UltraScale+ RFSOC Development Board

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  • Product Details
  • Product Specifications
  • Product Features and Applications
  • Shipping List
    • Commodity name: Low-Cost 8-Channel GEN3 Algorithm Verification and Evaluation Board
    • 型号: IWZU47DR_BL1156_8T8R

    IWZU47DR_BL1156_8T8R is based on the Zynq UltraScale+ RFSoC family device XCZU47DRFFVE1156 (hereinafter referred to as XCZU47DR). This series integrates key subsystems for multi‑band, multi‑standard cellular communications and cable infrastructure (DOCSIS) into a single SoC platform, featuring a feature‑rich 64‑bit quad‑core Arm® Cortex‑A53 processor and a dual‑core Arm Cortex‑R5F processing system. Zynq UltraScale+ devices combine an ARM Cortex‑A53 processing subsystem, UltraScale+ programmable logic, and industry‑leading signal‑processing bandwidth, enabling the implementation of complete RF signal chains to meet the demanding requirements of high‑performance RF applications such as wireless communications, cable TV access, and test & measurement.

    IWZU47DR_BL1156_8T8R is based on the Zynq UltraScale+ RFSoC family, specifically the XCZU47DRFFVE1156 (hereinafter referred to as XCZU47DR). This family integrates key subsystems for multi‑band, multi‑standard cellular wireless communications and wired infrastructure (DOCSIS) onto a single‑chip SoC platform, featuring a feature‑rich 64‑bit quad‑core Arm® Cortex‑A53 processor and a dual‑core Arm Cortex‑R5F processing system. Zynq UltraScale+ devices combine an ARM Cortex‑A53 processing subsystem, UltraScale+ programmable logic, and industry‑leading signal‑processing bandwidth, enabling the implementation of complete RF signal chains to meet the demanding requirements of high‑performance RF applications such as wireless communications, cable TV access, and test & measurement.

  • Performance Metrics

    Main chip

    ● XCZU47DR

    Size

    ● 230mm * 182mm

    Expand memory

    ● PS DDR4 64-bit, 4GB

    ● PL DDR4 32-bit, 4GB

    Storage

    ● Nor Flash 1Gbit *2

    ● SD Card*1

    eMMC

    ● PS eMMC 8 GB

    Ambient temperature requirements

    ● Operating temperature: -40°C to 70°C

    Expansion interface

    ● QSFP28*2

    ● RS422*1

    ● 1 Ethernet port

    ● DAC*8

    ● ADC*8

    Indicator light

    ● Two status indicator lights: INIT_B and DONE

    ● Two status indicator lights: PS_ERR_OUT and PS_ERR_STATUS

    Power consumption

    ● 60W (actual measured value, depending on the application)

    Board power supply

    ● 12V

  • Serial number

    Product Name

    Product model

    Quantity

    Accessories

    Quantity

    Unit

    Note

    1

    RFSOC Algorithm Verification and Evaluation Board

    IWZU47DR_BL1156_8T8R

    1

    Development board

    1

    pieces

     

    Cooling fan

    1

    pieces

    Installed

    SD card

    1

    pieces

     

    SMA cable

    8

    pieces

     

    Ethernet cable

    1

    pieces

     

    Type-C data cable

    1

    pieces

     

    Power adapter + power cable

    1

    pieces

     

    Data USB drive

    1

    portion

     

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