Literature Recommendation: An RFSoC FPGA–Based Millimeter-Wave Digital Beamforming Receiver for MIMO Communications
Release date:
2026-03
Preface
(This article’s data source: Florida International University, Department of Electrical and Computer Engineering.)
Inter-channel interference ( HERE ) It is a major challenge in evaluating multiple-input multiple-output systems; after employing orthogonal codes for code multiplexing, these codes are generated via RFSOC, demonstrating that… Low-power ultra-wideband ( UWB ) Beamforming The effectiveness. Experimental measurements show that beamforming performance and ICI suppression can reach 36 dB, with virtually no degradation in signal-to-noise ratio (SNR)—representing the highest clock frequency and ICI level achieved to date.
(This article’s data source: Florida International University, Department of Electrical and Computer Engineering.)
I. Overview
Current cellular technologies employ high frequencies (6–300 GHz) to enhance wireless link throughput and spectral efficiency. The 28–38 GHz band has attracted significant attention in 5G cellular mobile and backhaul communication systems; however, to leverage millimeter-wave spectrum more efficiently, numerous technical challenges must be addressed, with the primary one being— Significant path loss limits the long-range communication of millimeter waves. 。
Previous array architectures have included analog components, hybrid systems, and all-digital beamformers (DBFs). However, conventional digital beamformers require a dedicated analog-to-digital converter (ADC) and digital signal processor at each antenna element, which significantly increases… The hardware complexity, chip area, size, weight, and power consumption of MIMO applications.
Researchers have proposed a method that employs coded multiplexing technology. A four-channel digital beamformer, which has been experimentally validated on the RFSOC platform.
II. Structure of the Digital Beamformer
2.1 Code Reuse Receiver
The concept of code multiplexing for a single ADC receiver is illustrated in the figure, where signals from multiple antenna elements propagate through a shared path. One method for separating the signals in this shared path is to use Frequency Division Multiple Access (FDMA) . Furthermore, this approach leads to low spectral efficiency, as the bandwidth required for multiplexing signals is significantly greater than that of the transmitted signals. In addition, interference from adjacent channels will overlap with the combined paths, necessitating highly selective and costly equipment; the second option is Time Division Multiple Access ( TDM ) . Since the signals are not processed simultaneously, this reduces the achievable data rate. This is because TDM introduces processing latency. In contrast, Code multiplexing technology neither reduces the spectral efficiency of the wireless channel nor introduces latency. 。
Figure 1: Code Multiplexing Receiver (CMR) architecture: The input signal is encoded at baseband using a custom-designed encoder circuit board.
2.2 Receiver Design
The developers have validated this concept (as shown in Figure 1). The signal is initially transmitted via an ultra-wideband tightly coupled dipole array ( TCDA ) Acquisition. A direct‑conversion architecture is employed, with a low‑noise amplifier (LNA) placed after each antenna element to compensate for the noise contribution of subsequent stages.
The orthogonal WH code is generated using an RFSoC FPGA, and the received signal is then multiplied by the WH code. The chip rate of the code corresponds to the spread-spectrum bandwidth, with BWcode = Lc × B, where Lc is the code length and B is the bandwidth of the original received signal. Subsequently, the encoded signal is multiplexed into a single channel and fed to a single ADC. It is worth noting that: The composite signal is oversampled to prevent aliasing from adjacent channels, thereby satisfying the Nyquist sampling criterion. This is necessary because the overlap of aliased signals degrades signal quality. After digitization, a matched filter is applied to the decoded signal to correlate the recovered signal with the received signal, and beamforming is performed as a post-processing step.
3. Digital Platforms and Signal Extraction
In the digital baseband section, orthogonal Walsh–Hadamard (WH) codes are generated using the advanced Xilinx (now AMD) ZCU111 FPGA evaluation board. As previously described, these orthogonal codes are produced at clock frequencies of up to 400 MHz. The evaluation board integrates an XCZU28DR RF SoC chip, which includes eight 12-bit RF ADCs operating at a sampling rate of 4.096 GSPS, as well as eight 14-bit RF DACs with a sampling rate of 6.554 GSPS. Furthermore, the device incorporates both programmable logic (PL) and a processing system (PS) on the same platform.
|
RF-ADC |
8-channel acquisition; 12-bit, 4.096 GSPS |
|
RF-DAC |
8-channel transmission; 14-bit, 6.554 GSPS |
|
System Logic Cells |
930K |
|
DSP slices |
4272 |
|
Memory |
60.5Mb |
|
Maximum I/O pins |
371 |
Table 1: XCZU28DR Specifications
Signal extraction for each channel is performed on the FPGA. As previously mentioned, inter-channel interference signals occupy adjacent channels to the desired signal. Accordingly, the interference channel also spreads in bandwidth. Although the desired signal and the interfering signal overlap in the frequency spectrum, digital matched filtering can despread them, allowing the original signal to be accurately recovered. 。
Figure 2: Xi’an Birei Electronics—All‑Chinese‑Made 6U VPX High‑Speed Signal Processing Board
4. Setting Up the Experimental Environment
In the experimental demonstration, the developers utilized off-the-shelf components available on the market. Figure 3 illustrates the experimental setup used for measurement and data acquisition. At the transmitting end, a horn antenna with an output power of +10 dBm is connected to a signal generator. At the receiving end, a four-element tightly coupled dipole array (TCDA) is employed for reception. The bandpass filter following the array suppresses out-of-band reception, and the subsequent stages include a mixer and a local oscillator for downconverting the received signal. . Vector signal generator ( VSG ) It serves as the local oscillator and is connected to a 1:4 power divider, providing the LO signal to all four mixers. Subsequently, these four downconverted signals are encoded using a custom-designed Encoder Circuit Board (ECB). The encoding is generated by an FPGA board. An FPGA mezzanine card (FMC+ Vita 57.4, HTG) interfaces the FPGA board with the ECB.
Figure 3: Test platform built by developers using the ZCU111
A local host is connected to the FPGA via a high-speed Ethernet cable for programming and post-processing. The local host generates complex bitstreams and uploads them to the FPGA to program its internal structure. Subsequently, the combined output is displayed on an oscilloscope.
Figure 4: Power spectral density of 36 dB in Channel 1; power spectral density of 26 dB in Channel 2.
The primary objective of this work is to mitigate adjacent‑channel interference in MIMO systems. Figure 4 shows the power spectral density of the desired channel and that of the adjacent interfering signal. For proof of concept, measured data for both signals are presented. These measurements indicate that Channel 1 exhibits a maximum signal‑to‑interference ratio (SIR) of approximately 36 dB, while Channel 2 shows a value of about 26 dB. The developers observed that, because the MIMO measurement setup is hardware‑intensive, hardware imperfections introduce deviations in the channel SIR values. Non-ideal factors include coaxial cables, custom-designed encoder circuit boards, and adapter boards (used to bridge between the encoder board and the FPGA). The impact generated.
V. Conclusion
The developers have designed and validated a low-cost, low-power receiver architecture for MIMO applications that employs a single ADC, thereby significantly reducing the SWaP‑C footprint. Orthogonal WH codes enable multi-antenna multiplexing, thereby significantly enhancing spectral efficiency. The off-the-shelf RFSoC FPGA used in this demonstration supports a maximum clock frequency of 400 MHz. Furthermore, a measured signal‑interference ratio (SIR) of 36 dB was achieved, validating the proposed receiver’s interference‑suppression performance in multi‑user scenarios.
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