Preface

I. Introduction

Modern warfare demands that high‑tech radar systems possess high range resolution, robust anti‑jamming capabilities, and superior target detection performance. Digital technologies in radar systems enable digital beamforming, high‑quality signal generation, and flexible signal processing. At the same time, they allow… Radar waveform It can be flexibly adapted to suit various operational scenarios. Phased-array radar, which integrates phased-array antennas with digital technologies, is ideally suited for emergency applications and a wide range of use cases. Current array‑radar signal‑processing systems rely on discrete ADCs/DACs and multi‑stage microwave frequency conversion; for resource‑constrained applications, these often entail larger size, weight, and power consumption, while also demanding high sampling rates and wide bandwidths.

The AMD RFSoC features multiple DACs and ADCs operating at high sampling rates, incorporates MTS functionality to synchronize phased-array antennas, and can transmit large volumes of high‑speed sampled data without requiring additional external dedicated chips. . The aforementioned characteristics are sufficient to meet the radar performance requirements of modern phased-array radars.

This paper presents the design and implementation of a transceiver digital processor applicable to phased-array antenna systems comprising hybrid subarrays. The paper describes the TRDP architecture tailored to the system’s hardware configuration, as well as the system software architecture encompassing digital signal processing and beamforming, while also discussing the MTS design between subarrays. Furthermore, a testbed consisting of 81 subarrays was employed to demonstrate waveform generation, pulse compression results obtained through loopback testing, and receive‑side multi‑beamforming performance.

·Array Antenna System Architecture

The radar’s array antenna system architecture comprises three main components: the transmit/receive digital processor (TRDP), the radio frequency front end, and the antenna array. The system architecture is illustrated in the figure below.

The transmit/receive digital processor generates and receives intermediate-frequency signals and interfaces with the external controller to manage the entire array antenna system. It also performs digital signal processing, such as pulse compression for target detection and digital beamforming based on subarrays.

TRDP is composed of UltraScale+ RFSoC 、 A low-jitter clock converter 、 Intermediate-frequency interface analog circuitry and Voltage regulator composition In an array antenna system, multiple TRDPs are interconnected to the antenna control unit via optical links. The RF link is responsible for receiving and transmitting RF signals and provides up- and down-conversion functions according to the operating frequency band. When the frequency is below the C‑band, the TX/RX channels can be directly connected to the antenna array through filters, amplifiers, and interface circuits. The transmit/receive module (TRM) amplifies the TX signal and receives the return signal using a low-noise amplifier. The array antenna radiates RF signals and captures the return signals from the target. The antenna’s power gain and beamwidth are related to its directivity and effective aperture. To prevent grating lobes in the system’s coverage, an appropriate combination of element spacing and element count is required.

·Hardware Design of TRDP

As shown in the figure, The hardware architecture of a transmit/receive digital processor integrated with the ZU49DR RFSoC chip. This RFSoC incorporates high‑performance ADCs and DACs within a system‑on‑chip (SoC), replacing discrete data converters with an integrated direct RF sampling approach, and integrating high‑speed data links on the same die, thereby reducing power consumption and package size by 50–75%. Its 16 GSPS DAC and 8 GSPS ADC enable signal acquisition and transmission, while its wide analog bandwidth of 0–6 GHz and on‑chip digital upconverter ( DUC ) and the on-chip digital downconverter (DDC) can support direct RF input/output or intermediate-frequency input/output, enabling signal frequency conversion via up- and down-conversion. The RFSoC connects to DDR memory, allowing for high‑speed caching of large‑scale array data. 。

·Multi-tile and multi-chip synchronization

To achieve synchronization among chips in the TRDP, each TRDP employs an LMK04828 clock cleaner with low jitter and low timing skew, providing clocks to multiple RFSoCs and establishing a hardware foundation for synchronized operation across all channels in the system. The RFSoC circuitry utilizes a meticulous PCB layout and routing, and the external interface for IF signals employs 5 0-ohm microstrip lines, which can better ensure the consistency and isolation of multiple channels. The isolation between ADC channels, between DAC channels, and between ADC and DAC channels as well as the clock signal was tested separately. The test results show that, within the operating frequency range of 0 to 3 GHz, the inter-channel isolation exceeds −60 dBc.

· TRDP RFSoC Firmware Architecture Design

The firmware architecture encompasses I/O control, beam data exchange, waveform processing, the receive chain (RX chain), the transmit chain (TX chain), multi‑element synchronization, signal processing, and phased‑array digital multi‑beamforming. The I/O control module coordinates internal FIFOs and external devices—such as the radio frequency (RF) chain and the TRM—via a scheduler‑driven timing sequence. Beam data is exchanged over 10‑Gbps Aurora channels.

II. System Architecture Design

Waveform processing involves the generation and storage of baseband signal codes, based on radar parameters such as pulse width and signal bandwidth. The RX and TX chains handle intermediate-frequency signals in RF data processing. Prior to and following data conversion, an RF digital‑to‑analog converter (RFDC)—comprising multiple ADCs and DACs—performs operations like DUC, DDC, decimation, and interpolation, thereby realizing the RFSoC’s intermediate‑frequency architecture.

III. Testing

TRDP generates waveforms according to the controller’s commands and synchronizes them with the PRT, transmitting radar signals to the RF chain. Figure (a) shows the spectrum of an LFM signal with a bandwidth of 3 MHz and a pulse width of 10 µs. The LFM center frequency is converted to the X‑band by the RF chain and then measured. By routing the same signal back through the loop to the ADC, the pulse compression result—shown in Figure (b)—is obtained. Pulse compression is implemented in the frequency domain using the same method as Equation (3), with a Taylor weighting function employed to suppress time-domain sidelobes. The time-domain sidelobe level is approximately −37 dBc, and the mainlobe width is about 0.3 µs, satisfying the requirement of a pulse compression ratio of 30 and achieving a range resolution of 50 meters. TRDP is a board that digitizes both transmission and reception processes in array antenna systems composed of multiple subarrays. Depending on the number of channels and subarrays in the array antenna, multiple TRDPs may be used; phase synchronization among TRDPs is a critical factor determining the overall performance of the array antenna. Figure 6(c) presents the phase‑synchronization performance between TRDP channels, derived from simple statistical analysis. The blue line indicates the inter‑channel phase difference before performing MTS, with an average deviation of approximately 52.7°. In contrast, the orange line shows the inter‑channel phase difference after MTS, revealing a reduction of 8.3° in the phase mismatch.

IV. Conclusion

The developers designed and implemented a transceiver digital processor for array antenna systems and validated its performance in radar applications, including waveform generation, pulse compression, and digital beamforming. The RFSoC’s capabilities within the TRDP are sufficient to meet the requirements of array‑antenna design, and its programmable logic enables the implementation of high‑resolution radar waveforms, digital beamforming, and pulse compression.