Literature Review: RFSoC Applications — A Radiation-Measurement Front-End Based on Pulse Monitoring
Release date:
2026-03
Preface
Pulse monitoring plays a fundamental role in particle and nuclear physics as well as in radiation measurement. To extract the maximum information from these pulses, Acquire pulse waveform It is a key objective. Radiation measurement relies on pulse monitoring, which can be implemented using various high-speed analog-to-digital converters (ADCs) and field-programmable gate array (FPGA) configurations. RFSoC can achieve optimal… Power consumption 、 Design the simplicity, System the flexibility as well as the digital signal processing (DSP) of Usability 。
1. Feasibility
In the RFSoC, the ADC exhibits a flat frequency response across the 1–125 MHz range—without any digital signal processing, the root-mean-square (RMS) noise level is 2.1 ADC counts. Digital signal processing reduces the RMS noise level to 0.8 ADC counts. (The input equivalent noise is 40 μVrms ) Baseline correction via digital signal processing can effectively prevent overcharging of the photomultiplier tube following large pulses. Between all channels, Crosstalk is below -55 dB. The measured data transmission speed can support a trigger rate of up to 32 kHz (corresponding to a data rate of 750 Mbps). Overall, Electronic devices based on RFSOC are well suited for pulse monitoring. , after some modifications, the Kamioka Liquid Scintillator Antineutrino Detector (KamLAND) (Note: This detector is located underground at the Kamioka Mine in Gifu Prefecture, Japan, and is a large-scale neutrino detection apparatus situated at the same site as the Super-Kamiokande detector, holding an important position in the field of neutrino physics).
2. Addressing the Need for Pulse Monitoring
In most cases, ADCs digitize analog waveforms at sampling rates ranging from 50 MS/s to 1 GS/s and with resolutions of 8 to 12 bits. FPGAs are primarily used to control and read the ADCs and to transfer the digitized waveforms to a host computer. To increase the sampling rate, dedicated integrated circuits are typically employed. For example, the Domino Ring Sampling (DRS4) chip. However, DRS4 is not well suited for dead-time‑free measurements. In cosmic particle physics, time-of-flight measurements without dead time are of great significance, particularly in experiments probing rare processes such as neutrinos, dark matter, and neutrinoless double-beta decay. This is because certain background discrimination strategies require capturing pulses that are very close in time.
Accordingly, many rare-event search experiments have designed custom electronic systems. Similarly, a zero-dead-time front-end electronics system was developed and implemented in the KamLAND liquid scintillator antineutrino detector. However, this front-end electronics system… Buffer capacity 、 Read speed and Digital Processing Resources There are limitations in this regard. These constraints hinder the detection efficiency of neutrons produced by cosmic-ray spallation. To improve neutron detection efficiency, it is necessary to correct for waveform overshoot and to… Sufficient buffer capacity and High throughput Reading out captures all pulses generated, including afterpulses. Combined with advanced software processing on the backend computer, this approach can deliver improved neutron detection efficiency. Furthermore, in… Power and cooling resources are limited. In such an environment, power consumption also imposes additional constraints.
RFSoC technology was developed to address this issue; compared with the conventional techniques discussed earlier, the application of RFSoC technology… 有望实现无死区时间脉冲监测 ， Especially in the KamLAND‑Zen experiment. It features high‑speed data transmission that can easily support 1 GbE or 10 GbE, straightforward handling of external and/or internal memory, low power consumption thanks to the tight integration between the ADC and the PL, as well as a large number of logic cells and digital signal processors. RFSoC has begun to enter the realm of physical experiments, used for controlling superconducting qubits and extracting data from them. 。
3. Prototype Design
In pulse‑monitoring applications, the analog‑to‑digital conversion rate must exceed 1 GS/s to enable vertex reconstruction and particle identification for SPE events. A single ADC cannot accommodate the dynamic range spanning from single‑PE events to large muon events at this noise level. Consequently, each PMT analog input is split into a high‑gain (h‑gain) channel—used to process signals from a few tens of PE events—and a low‑gain (l‑gain) channel—used to handle muon events. To prevent charge loss, analog and digital electronic devices must maintain a platform frequency response of up to approximately 60 MHz. 。
The primary goal of the front-end electronics is to enhance neutron detection efficiency, leveraging a 1 GS/s ADC, FPGA configuration, and an 8-channel RFSoC. The former will inevitably… This leads to increased power consumption, and coordinating timing among multiple ADCs and the FPGA at a 1 GS/s sampling rate presents significant challenges. The latter option would either increase or decrease the number of boards, or it would raise the number of RFSoCs per board—neither of which is cost‑effective for handling a total of 2,000 PMTs. Therefore, the 16‑channel RFSoC is the most suitable choice.
The board is equipped with a single RFSoC (XCZU29DR-1FFVF1760E), which integrates 16 RF‑ADCs with 12‑bit resolution and a maximum sampling rate of 2.058 GS/s, along with 16 RF‑DACs featuring 14‑bit resolution and a maximum sampling rate of 6.554 GS/s. . This RFSoC also integrates 930,300 logic units 、 4,272 digital signal processing units (DSPs) , one quad-core Arm Cortex-A53 and one dual-core Arm Cortex-R5. Both the PS and PL domains each integrate 4 GB of double-data-rate (DDR) synchronous dynamic random-access memory (SDRAM).
3.1 Programmable Logic
The PL data flow is shown in the figure; the RF‑ADC is configured to operate at 2 GS/s and employs a ×2 decimation, thereby achieving an effective overall sampling rate of 1 GS/s. Each RF‑ADC output conforms to the Advanced eXtensible Interface 4‑stream (AXI4‑stream) standard. At a clock frequency of 125 MHz, the data width (TDATA) is 128 bits (8 samples × 16 bits). The valid signal (TVALID) is generated simultaneously by the RF‑ADC. It is worth noting that, Xilinx guarantees the high 12 bits of the RF‑ADC output. The low 4 bits are truncated, and the remaining bits are routed through the digital signal processing (DSP) module. 。
3.2 DSP Module
The DSP module performs baseline restoration (BLR) and digital filtering. BLR is designed to eliminate waveform overshoot following large pulses. By in… Calculating a 64‑ns moving average over the negative portion of the waveform can effectively mitigate this overshoot. . Subtract this moving average from the raw digitized waveform to generate the BLR waveform. The conceptual diagram of BLR is shown in the figure below:
3.3 Processing System
The PS includes a quad-core Arm Cortex‑A53 processor; it reads data from the PL and transmits it to the host computer via a 1 GbE link, which is implemented using a Gigabit Ethernet MAC module with multiplexed input/output.
4. Summary
RFSoC technology represents cutting-edge advancements in signal processing and data acquisition. This prototype demonstrates an easily interpretable frequency response, low… Noise (approximately 40 μVrms), linearity within ±2%, and low crosstalk (< 55 dB) , as well as when using Stable data transmission at a trigger rate of up to 36 kHz (750 Mbps) with 16 inputs and a power consumption of 43 W. The DSP module has been shown to effectively correct PMT overshoot. Furthermore, the system’s power consumption has demonstrated a significant advantage over conventional FPGA‑plus‑ADC architectures. This study provides strong evidence of the feasibility and potential of employing an RFSoC‑based approach for pulse monitoring.
Keywords:
Contact Us
Phone:+86-29-84508304
Website: www.interwiser.com
Address: 25th Floor, Building E, Xidian Science & Technology Park, No. 168 Kechuang Road, Yanta District, Xi'an City
