Collins’ ORCHA—System-in-Package Based on RFSoC
Release date:
2026-03
Collins Aerospace is a long-standing provider of reliable weather radar systems for pilots, ensuring the safety of air travelers. Collins Aerospace has developed a flexible… 2–18 GHz Digital Beamforming Building Blocks —This is a multi-board solution, consisting of a reconfigurable SiGe transceiver and Xilinx RFSoC It comprises a data converter and a digital beamforming engine.
Collins has demonstrated the feasibility of pairing a universal module with a low-cost, dual-polarized S-band antenna array for multi-beam digital beamforming. Building on this experience and recent advances in microelectronics, Collins is developing ORCHA (Opensystems RFSoC Hybrid Assembly). ORCHA is a highly integrated system-level package. , in fact includes Xilinx RFSoC And all supported electronic components, power conversion, memory, and clock generation are integrated into a compact package.
1. Digital System
ORCHA aims to simplify Retractable radar and RF system Design and assembly:
- ORCHA can support a system that may include Hundreds of RF channels
- The third-generation RFSoC can now directly sample up to 6GHz RF signals, thus eliminating the need for frequency up- and down-conversion stages used in S‑Band radar systems.
- ORCHA receives the DAC sampling clock ( Several GHz ) or a lower-frequency clock ( Several hundred MHz ) as the reference clock for the RFSoC
Supports multiple ORCHA systems Synchronous Data Converter Sampling Clock
2. Digital Processing Architecture
A major challenge of the fully digital phased-array concept is the need to transmit and process vast amounts of data. Each ORCHA SiP can generate up to Raw sample data with an instantaneous bandwidth of 500 MHz For example, assuming a minimum sampling rate of 1.33 GSPS and 16 bits per sample, each antenna channel can generate 21.28 Gbit/s of data. This means that for a single polarization, each… The DPPAR panel can generate 1.36 Tbit/s. of the data. This type of processing is challenging and requires addressing data sparsity or other innovative approaches.
Accordingly, the DPPAR is designed to perform most of the necessary computations directly on the array. This both reduces the amount of off‑array signal processing required and lowers the overall data volume. To achieve this, SiPs must provide three key functions: Local data processing, global data organization, and data management 。
The FPGA logic resources built into Sip provide on‑chip processing. The purpose of on‑chip processing is to… Separate management The input and output of each antenna element have their instantaneous bandwidth adjusted as needed. At this stage, only waveform/antenna management functions are provided, such as antenna calibration, downsampling, direct digital synthesis of the transmit waveform, and pulse compression. Each FPGA contains 16 replicated copies of the local processing system. As shown in the figure below:
Figure 1: Example of Local Processing Configuration
Figure 2: Performance of the Selected FPGA
To enable global processing, SiPs must be able to communicate with other SiPs as well as with off‑array systems, such as radar signal processors. To facilitate this, SiPs have been networked into a mesh architecture. This entails interfacing with… Recently, the neighbor’s high-speed data connection. , as shown in Figure 3, wherein The blue arrows indicate panel-to-panel connections. , black The colored arrows indicate local SIP-to-SIP connections routed via dedicated traces on the backplane circuit board. . Panel-to-panel connections are also established in a similar manner, utilizing connectors located along the perimeter of each panel. These peripheral connectors can also serve as connection points between the array and external systems. Multiple links may be employed to enable several systems to connect to a single array.
Figure 3: Network Connectivity from SiP to SiP
Data and Command/Control Information These connections between SiPs are used to transmit data via routing logic programmed on each SIP.
By integrating on-board Beamforming 、 Intelligent Data Routing and Adjustable Instantaneous Bandwidth , which can more effectively utilize the available bandwidth on each physical link; furthermore, for a single beam, underutilized physical connections can be leveraged, enabling the network to simultaneously handle additional beams. For example, using the preceding… Nyquist sampling of a 500 MHz signal An example, using only the array on Beamforming can generate five simultaneous beams. If the instantaneous bandwidth of each beam is reduced, the number of concurrent beams increases accordingly.
In addition to providing data‑conversion capabilities, the RFSoC also offers on‑array signal‑processing functionality. This capability can be used to reduce the volume of raw data delivered from the array through decimation and/or to compute application‑specific metrics, such as those required for radar or communications monitoring.
Currently, the RFSoC single-chip (Zynq UltraScale+ XCZU49DR) can support a single board 1. 6-channel ADC (14-bit, 2.5 Gsps) ports, 16-channel DAC (14-bit, 9.85 Gsps) ports. Xi’an Birei Electronic Technology offers a solution that uses a demo project to illustrate how to configure and orchestrate the multi‑tile synchronization (MTS) of channels across multiple high‑speed acquisition daughter boards, ensuring a stable inter‑channel sampling phase offset after each power‑up. RFSoC multi‑board synchronization leverages hardware–software co‑design to achieve clock‑phase alignment and trigger synchronization among multiple RF‑SoC boards, guaranteeing coordinated operation of the ADCs and DACs on each board with picosecond‑level precision. This technology addresses several key challenges in distributed RF systems—such as the “timing mismatch problem”—and serves as a foundational enabler for modern high‑precision RF applications.
RFSoC multi‑board synchronization technology leverages hardware–software co‑design to achieve clock phase alignment and trigger synchronization across multiple RF system‑on‑chip boards, ensuring that the ADCs and DACs on each board operate in concert with picosecond‑level precision. This technology addresses several key challenges in distributed RF systems, such as the “timing mismatch problem,” and serves as a critical infrastructure for modern high‑precision RF applications.
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