III. Architecture Design and Division of Labor

The data processed by the RFSoC is transmitted to the Jetson module via the PCIe Gen bus. Inside the Jetson, ARM processor It handles the overall system scheduling and application logic, while the GPU leverages… CUDA Parallel architecture for executing AI inference tasks For example, the Jetson AGX Orin is equipped with 2,048 CUDA cores and 64 Tensor cores, delivering 275 TOPS of INT8 inference performance and enabling on‑device operation. Modern AI models such as Transformers.

Figure 3: RFSoC+GPU Integrated High-Bandwidth RF Intelligent Processing Module

Jetson side:

2,048 CUDA cores + 64 Tensor cores, with INT8 performance of 275 TOPS.

12-core ARM Cortex-A78AE

32/64 GB LPDDR memory, with a bandwidth of 204.8 GB/s

Figure 4: Jetson AGX Orin Module

Interconnectivity and Data Flow:

The IQ data preprocessed by the RFSoC is transmitted to the Jetson via PCIe Gen4 x8 (with a theoretical bandwidth of approximately 16 GB/s). Under a typical configuration, the data rate of the 8‑channel ADC, after decimation, can be kept within the PCIe bandwidth limit. The Jetson inference results can be fed back to the RFSoC for closed-loop adjustments, such as interference mitigation or beam‑steering updates.

IV. Product Features

1. RF direct-sampling architecture eliminates analog-chain bottlenecks.

Compared to traditional Superheterodyne receiver The scheme, employing direct RF sampling technology, eliminates analog processing stages such as mixing, filtering, and intermediate-frequency sampling, thereby significantly reducing… Signal chain latency is reduced, lowering system power consumption and hardware complexity. 。

2. Division of Labor and Collaborative Operation Between FPGA-Based Real-Time Preprocessing and AI Inference

Pulse compression When algorithms such as digital beamforming and constant false alarm rate (CFAR) detection are implemented on an FPGA, processing latency can be kept at the microsecond level or even sub-microsecond level. By contrast, the Jetson GPU excels at handling computationally intensive tasks rather than latency‑sensitive ones. This clear division of labor enables the system to both… Meet real-time constraints , and also possesses strong Intelligent analysis capability 。

3. PCIe Gen4 x8 high-speed interconnect, ensuring data throughput.

The PCIe Gen4 x8 link between the RFSoC and the Jetson provides a theoretical bandwidth of approximately 16 GB/s. Raw IQ data from the 8‑channel ADC—calculated at 5 GSPS with 14‑bit resolution, yielding a theoretical data rate of about 70 Gb/s—is processed through the FPGA’s DDC and decimation stages, The data rate can be reduced to 1/40 of the original rate. , meeting the transmission capacity requirements of the PCIe link.

4. High-speed data recording and playback capability

The platform supports simultaneous continuous acquisition and recording of eight channels, and, combined with the DAC‑side playback function, enables closed-loop testing and scenario reproduction of RF signals. In practical system tests, under typical frequency bands, the transmit EVM is better than 1%. Phase coherence across channels meets picosecond-level synchronization accuracy. The requirements apply to systems such as phased-array radars that impose stringent constraints on channel consistency.

5. Modular design, easy to expand

The RFSoC core board and the Jetson core board adopt a separate, modular design, allowing users to select based on their computational power requirements. Replace with a different Jetson module, or select a different RFSoC model based on channel requirements. The system supports cascaded synchronization across multiple boards and, via an external clock distribution, can synchronize the ADC/DAC channels of several boards to picosecond-level precision, enabling scalable large‑scale array systems with 16, 32, or 64 channels.

V. Application Scenarios

Phased-array radar digital backend

The XCZU47DR achieves synchronous data acquisition across eight channels (with additional channels available when multiple boards are cascaded) and implements digital beamforming, while the Jetson platform runs object detection, trajectory tracking, and classification. Compared with the traditional “ADC + server” architecture, this solution features a higher level of system integration and shorter data transmission paths. 。

Electronic Warfare

The RFSoC performs real-time, full‑band scanning to extract time–frequency features from signals; the Jetson platform leverages deep learning models to classify threat types—such as frequency‑modulated signals and radar waveforms—and to generate jamming or deception strategies. The FPGA ensures low‑latency processing, while the GPU delivers high‑throughput inference; together, they are coordinated to meet the dynamic response requirements of adversarial environments.

5G Massive MIMO Prototype Verification

The single board provides 8-channel transmit/receive capability, Multi-board-level interconnects can be scaled to 32 or 64 channels, making them suitable for baseband processing in large-scale antenna arrays. . On the Jetson edge, AI models for beam management, user scheduling, and channel prediction can be deployed, leveraging TensorRT to accelerate real-time decision-making.

Spectrum Sensing and Intelligent Signal Processing

With continuous wideband capture capability spanning 1 MHz to 6 GHz, and paired with signal classification and emitter fingerprint‑recognition models running on the Jetson platform, a closed‑loop workflow—from detection to identification—can be executed at the edge, eliminating reliance on cloud servers.

Satellite communication terminal

The integrated design meets the requirements of end‑device applications with stringent size, weight, and power (SWaP) constraints. The RFSoC handles uplink and downlink frequency conversion as well as baseband processing for the protocol stack, while the Jetson platform runs link‑adaptation algorithms and manages traffic flows, supporting 100G Ethernet and PCIe expansion interfaces.

This issue’s product recommendation: