I. Introduction

The use of phased arrays, through beamforming and beam steering techniques, enables radiation to be focused in desired spatial directions. This provides the system with higher antenna gain in both transmission and reception, thereby improving link performance. When in-band full-duplex (IBFD) technology is applied to such arrays, they can simultaneously support multiple applications, including integrated sensing and communication (ISAC) capabilities. IBFD, also known as simultaneous transmit and receive (STAR), represents an emerging technology that breaks with traditional spectrum‑sharing paradigms, allowing devices to transmit and receive concurrently on the same frequency. This capability can only be realized when the device’s transmitted signal is suppressed to a level equal to or below the noise floor of its receiver—a process referred to as self‑interference cancellation.

For phased arrays and other directional/omnidirectional IBFD systems, sufficient SIC can be achieved by leveraging a variety of techniques across the propagation, analog, and digital domains within a given transceiver architecture.

For an array with a single antenna aperture, the combination of these SIC techniques enables IBFD operation at either the aperture level or the element level. While the latter approach allows for full utilization of both transmit and receive apertures, it requires high‑intensity SIC on each individual element, which often severely degrades the array’s output power and noise figure.

Figure 1: Example of an aperture-level IBFD array with (a) transmit and receive subarrays and (b) dedicated transmit subarrays further partitioned according to radar and communication functions.

II. Array Operations

Figure 2: The IBFD concept at the aperture level, highlighting three distinct SIC techniques: adaptive transmit and receive digital beamforming, and reference-based digital cancellation.

Figure 2 illustrates the operational concept of an IBFD array at the aperture level. The figure shows two transmitting elements on the left and two receiving elements on the right, but it can be adapted to arrays of any size or dimension. When the transmitter is active, a portion of the transmitted signal leaks into nearby receiving elements, generating self‑interference (SI) that, at moderate output power, can saturate the receiver. To prevent saturation, this aperture‑level architecture can employ one of three distinct self‑interference cancellation (SIC) techniques: adaptive transmit beamforming. This digital processing step involves weighting the data samples from each independent transmit channel so as to create a near‑field null in the direction of the receiving elements on the array. Upon optimization, this approach preserves the desired far‑field radiation pattern while reducing the strength of the transmitted signal, enabling linear processing and digitization at each receiving element.

III. Array System

The limitation of the array concept lies in the fact that small-scale prototypes cannot easily scale up by adding more elements. Three core technologies have previously been identified to enhance the scalability of these arrays: all-digital design, transmit/receive (T/R) modules, and beamforming/cancellation algorithms. These components can be integrated within a scalable panel‑based architecture, as illustrated in the exploded view shown in Figure 3.

Figure 3: Exploded view of the scalable array board, highlighting the aperture plate, the backplane PCB assembly, and the thermal management cold plate between them.

The figure illustrates the main components: the aperture‑plate assembly, which incorporates a T/R module mounted on its rear side (not visible in the photograph), and the backplane assembly, which houses the DC power regulation circuitry as well as an RF SoC integrating data converters and signal processors. Between these two lies a critical cold plate, serving as a thermal management solution to dissipate heat from the components on both the aperture plate and the backplane.

The following provides a detailed analysis of each component of the array system:

3.1 Aperture Assembly

The aperture assembly serves to interface the array’s electronic components with the surrounding environment, transmitting signals and receiving data. To this end, it comprises radiating elements arranged in an 8×8 square grid, totaling 64 elements. These elements are designed with a dual-polarization stacked-chip architecture, as shown at the top of Figure 4.

The electromagnetic model of the dual‑polarized antenna radiating element, illustrating how it is integrated into an 8×8 array and how the T/R module is mounted within the grid spacing.

3.2 Cold Plate

To support the ISAC project, it may be necessary to operate the array hardware at a higher duty cycle compared to conventional radar‑only applications, where the transmitter is active for only about 10% of the total time. Increasing the transmit duty cycle raises the overall steady‑state thermal load, as the duration of heat generation is extended. This necessitates a thorough analysis of thermal dissipation across the array to ensure that all components remain below their maximum junction temperatures and to prevent damage. To this end, a cold plate has been researched and designed to provide cooling for the array’s components under various thermal conditions.

Figure 6: Thermal model showing the array temperature differences under the assigned thermal‑element values, in degrees Celsius (a) for the left half only and (b) for the entire panel.

Figure 7: Mechanical model of a cold plate that extracts heat from a panel by leveraging the flow of liquid in vertical channels (with 16 rectangular slots for connecting holes to the backplate).

3.3 Backplane

The final key component of the array panel stack is the backplane PCB, which manages the subarray partitioning and its associated functions. The backplane leverages eight RFSoC devices, each interconnected with its nearest neighbors, as shown in Figure 8. For this design, the selected RFSoC version features 16 channels, each equipped with an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC), integrating a total of 32 data converters within a single package.

Figure 9 shows the side-by-side interconnection of two panels, indicating that the high-speed data interface not only links the RFSoCs on each panel but also connects the RFSoCs across panels. This architecture establishes a scalable digital mesh network composed of multiple processing nodes—namely, the RFSoCs—and enables simultaneous parallel processing of distinct computational threads. The concept is illustrated in the lower portion of the figure: for instance, two data streams are first processed on the board into array beams directed in different directions before being routed to a host computer for further analysis. This parallel on-board processing capability proves highly advantageous in ISAC applications, particularly when the array is partitioned as shown in Figure 1b and requires concurrent computation of multiple functional data streams.

Figure 8: Backplane circuit board assembly, highlighting the connections between each RFSoC and the eight units on the array, as well as the interconnections among them.

Figure 9: Interconnection of two backplane panels, demonstrating scalable inter-panel connectivity and parallel on-board processing capabilities.

4. Conclusion

IBFD phased‑array antennas can achieve isolation between the transmit and receive subarrays through a combination of digital SIC techniques. These phased arrays, along with their associated SIC processing methods, can be designed to be scalable, enabling the creation of arrays of arbitrary size. The key to this scalability lies in the architecture of the array system, which has already been discussed in the context of a panel‑based design. The aperture and backplane PCB components, as well as the cold‑plate thermal management solution, are highlighted as critical elements of the scalable approach, capable of operating across a frequency range of 2.7 GHz to … Future work will involve fabricating multiple array‑panel prototypes to validate their functionality while demonstrating diverse applications, such as ISAC.

Conclusion

It interfaces with eight array elements to support all 16 channels of the dual‑polarized radiators described earlier. In addition to providing data‑conversion functionality, the RFSoC also offers on‑array signal‑processing capabilities. This feature can be used to reduce the raw data volume delivered from the panel through downsampling and/or to compute application‑specific metrics, such as those required for radar or communication‑based detection.

Currently, the RFSoC single‑chip solution (Zynq UltraScale+ XCZU49DR) supports a single board with 16 ADC channels (14‑bit, 2.5 Gsps) and 16 DAC channels (14‑bit, 9.85 Gsps). Xi’an Birei Electronic Technology offers a solution that uses a demo project to illustrate how to configure and orchestrate each high‑speed acquisition daughter board to implement multi‑tile synchronization (MTS) across channels, thereby achieving stable inter‑channel sampling phase offsets after every power‑up. The RFSoC multi‑board synchronization technology leverages hardware–software co‑design to align clock phases and synchronize triggers among multiple RF‑SoC boards, ensuring that the ADCs and DACs on each board operate in concert with picosecond‑level precision. This technology addresses numerous challenges—such as the “timing mismatch” issue—in distributed RF systems and serves as a critical infrastructure for modern high‑precision RF applications.

The two figures above illustrate that, after a single board is equipped with one XCZU49DR IC, multi-board synchronization technology—enabling a single clock board to synchronize up to seven signal-processing boards—allows the system to scale to 32, 64, 128, or 256 channels while maintaining picosecond‑level synchronization across all channels. This approach has found widespread application in radar signal processing and communications monitoring.

Through picosecond‑level precision coordination, distributed RF systems are breaking through performance barriers. From the high‑accuracy scanning of phased‑array radars to the ultra‑precise control in quantum computing, and from the massive antenna arrays of 5G base stations to the cosmic observations made by radio telescopes, this technology is reshaping how we connect with, perceive, and explore the world.